1. Field of the Invention
The present invention relates to a wafer test method, for testing chips in a semiconductor wafer, that are used in manufacture of semiconductor devices and, more particularly, to a test method of chips in which a statistical technique is employed in a test algorithm.
2. Background Art
A wafer test method, i.e. a test method of chips in a wafer, in which a good/defective judgment on untested chips is performed after testing of sample chips on a semiconductor wafer, usually employs a sampling test. Such kind of test method is disclosed in, for instance, (a) Japanese Unexamined Patent Publication No. 8-274139, (b) Japanese Unexamined Patent Publication No. 60-42664, or (c) Japanese Unexamined Patent Publication No. 5-267417. In the publication (a), a good chip ratio of a single wafer is determined and a wafer-by-wafer good/defective judgment and a good/defective judgment on a wafer lot are performed based on yield data of test results of sample chips. In the publication (b), good/defective judgments are performed in the same manner as in the publication (a) based on statistical data of past lots, such as characteristic values of respective test items, and reference values. In the publication (c), after the start of skipped monitoring, judgments of test items with which the skipping can be continued are performed by comparing test results of all items of several sample chips per wafer with reference yield values. Since tests on wafers, lots, and test items that have been judged to be good are omitted thereafter, this wafer test method provides an advantage that the test time can be shortened.
The sampling tests of the above-described conventional techniques employ test methods in which a good/defective judgment on untested chips is performed by using the yield that is obtained through averaging with the number of all chips on a wafer or the total chip area and is hence what is called a macroscopic index. Therefore, when defective chips are concentrated in a particular region on a wafer, the accuracy of the good/defective judgment becomes low. This causes a problem that the sampling ratio cannot be reduced.
To investigate a proper method for improving process capabilities in terms of quality assurance of materials, a manufacturing process, and manufacturing facilities that are factors of causing defective chips based on sampling test results, it is necessary to recognize microscopic relative positional relationships between sample chips and untested chips to be subjected to a good/defective judgment. However, a relative positional relationships between sample chips and untested chips to be subjected to a good/defective judgment is not considered in the conventional techniques.